1. show the relationship between Vds-Ids fot MOSFET.
2. show how its characteristics it varies with i. increasing Vgs ii) velocity saturation iii) Channel length modulation iv ) W/L ratio.
3. Describe body effect also write mathematical expression?
4. Explain briefly latch up effect in CMOS design and how will you overcome this effect?
5. Explain Noise Margin with the help of inverter?
6. how delay varies on increase load capacitance?
7. how to minimize power consumption for CMOS logic?
8. What will happen when the interchanged PMOS and NMOS with one another in an inverter?
9. Explain body effect?
10. What is advantage of NAND over NOR gate in fabrication?
11. Explain briefly Noise Margin and how to determine Noise Margin ?
12. Explain inverter sizing?
13. How do you size NMOS and PMOS transistors to increase the threshold voltage?
14. if we include a resistance at the output of a CMOS circuit, what will happen?
15. Explain limitations of increasing the power to reduce delay?
16 How does metal Resistance ovary with increasing thickness and length?
17. Explain Charge Sharing and its problem while sampling data from Bus?
18 we need increase the size of inverters in buffer design, why? Explain why we cannot give the output of a circuit to one large inverter?
19. With Mathematical expression, explain CMOS switching power dissipation?
20 Why substrate in NMOS connected to ground and PMOS to VDD?
21 What are the difference b/w a MOSFET and BJT ?
22. Which type transistor has more gain- BJT or MOS and explain with suitable reason?
23 Why does PMOS and NMOS are equally size in a Transmission Gates?
24 Explain metastability, how it will occur? What are different methods to avoid this?
25 what is zener breakdown?
26 what is avalanche breakdown?
27 if Vds is increased over saturation, then what will happen?
2. show how its characteristics it varies with i. increasing Vgs ii) velocity saturation iii) Channel length modulation iv ) W/L ratio.
3. Describe body effect also write mathematical expression?
4. Explain briefly latch up effect in CMOS design and how will you overcome this effect?
5. Explain Noise Margin with the help of inverter?
6. how delay varies on increase load capacitance?
7. how to minimize power consumption for CMOS logic?
8. What will happen when the interchanged PMOS and NMOS with one another in an inverter?
9. Explain body effect?
10. What is advantage of NAND over NOR gate in fabrication?
11. Explain briefly Noise Margin and how to determine Noise Margin ?
12. Explain inverter sizing?
13. How do you size NMOS and PMOS transistors to increase the threshold voltage?
14. if we include a resistance at the output of a CMOS circuit, what will happen?
15. Explain limitations of increasing the power to reduce delay?
16 How does metal Resistance ovary with increasing thickness and length?
17. Explain Charge Sharing and its problem while sampling data from Bus?
18 we need increase the size of inverters in buffer design, why? Explain why we cannot give the output of a circuit to one large inverter?
19. With Mathematical expression, explain CMOS switching power dissipation?
20 Why substrate in NMOS connected to ground and PMOS to VDD?
21 What are the difference b/w a MOSFET and BJT ?
22. Which type transistor has more gain- BJT or MOS and explain with suitable reason?
23 Why does PMOS and NMOS are equally size in a Transmission Gates?
24 Explain metastability, how it will occur? What are different methods to avoid this?
25 what is zener breakdown?
26 what is avalanche breakdown?
27 if Vds is increased over saturation, then what will happen?
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