Physical Design Interview Questions Part 2

1. What is the use of double spacing and multiple vias? 

2. How buffer insertion on victim net can help avoid crosstalk? 

3. What is the difference between top level Chip Design and Block level design? 

4.How will you place macros in a full chip design? 

5. Explain Hierarchical Design and flat design? list down all differences between them.

6. How does design complexity increases, when the operating frequency of the design increases? 

7. Have you done physical verification, what all physical design tools you used? 

8. How will solve  routing congestion exists between  macros? 

9. on what parameters does die size depends on? 

10. What is antenna effect, how can it create problem in design? 

11. If the full chip design is routed by 7 layer metal, why macros are designed using 5 metal layer instead of using 7 metal layer? 

12. what is the technology node of your project?

13.  what is the block  size?

14. How many metal layers were there

15. what is the  technology nodes, on which you have hands on experience in?

16. What is the hard macros count in your design? 

17. What all inputs required to start physical design flow? 

18. What is synopsys design constraint (SDC)  file contains? 

19. Explain the power structure of your design? 

20 How will you  calculate , macro ring width and strap or trunk width, core ring width?  

21. How will you do power planning?)

22. How to find number of power pad and IO power pads? 

23. How the width of metal and number of straps calculated for power and ground?

Physical Design Interview Question Part 1

1.what all low power techniques you know? 
2.how would you control leakage current? 
3.what are the ways to reduce dynamic power consumption? 
4.What are the factor does dynamic power depends? 
5.How will you do power planning? 
6.How to estimate the static power
7.How to estimate the dynamic power
8.The number of the core power pad required for each side of the chip core PG ring width
9. How to  EM & IR are taken care during power planning stage?
10. How will you handle IR drop and congestion which occurring at the same time ? 
11. what are the different methods to reduce  IR drop problem? 
12. How will you fix setup time problem in reg to reg path?
13. How insertion of buffer help in fixing setup time violation?
14. what all the parameter you will see to qualify floorplan? 
15. what do you mean by Aspect ratio? 
16. what are the guidelines you will follow for Macro placement 
17. what all the challenges you faced in you P&R flow? 
18.  Explain briefly How to synthesize clock tree, ? 
19. How many clocks were present in your  project? 
20. What all complexity you faced  to handle those clocks? 
21. Are they come from seperate external resources or PLL? 
22. Why buffers are used in clock tree? 
23. What do mean by crosstalk cross talk, How to prevent cross talk effect? 
24.What is shielding ? how it helps to avoids crosstalk? 
25. How do spacing  reduces crosstalk effect? 

Moore's Law

Moore's law is the observation that the number of transistors in a dense integrated circuit doubles approximately every two years. The observation is named after Gordon E. Moore, the co-founder of Intel and Fairchild Semiconductor, whose 1965 paper described a doubling every year in the number of components per integrated circuit, and projected this rate of growth would continue for at least another decade. In 1975, looking forward to the next decade,he revised the forecast to doubling every two years.

His prediction proved accurate for several decades, and the law was used in the semiconductor industry to guide long-term planning and to set targets for research and development. Advancements in digital electronics are strongly linked to Moore's law: quality-adjusted microprocessor prices, memory capacity, sensors and even the number and size of pixels in digital cameras.

Digital electronics have contributed to world economic growth in the late twentieth and early twenty-first centuries.Moore's law describes a driving force of technological and social change, productivity, and economic growth.

The period is often quoted as 18 months because of Intel executive David House, who predicted that chip performance would double every 18 months (being a combination of the effect of more transistors and the transistors being faster).

"Moore's law" should be considered an observation or projection and obviously not a physical or natural law. Although the rate held steady from 1975 until around 2012, the rate was faster during the first decade. In general, it is not logically sound to extrapolate from the historical growth rate into the indefinite future. For example, the 2010 update to the International Technology Roadmap for Semiconductors, predicted that growth would slow around 2013, and Gordon Moore in 2015 foresaw that the rate of progress would reach saturation: "I see Moore’s law dying here in the next decade or so."

Intel confirmed in 2015 that the pace of advancement has slowed, starting at the 22 nm feature width around 2012, and continuing at 14 nm. Brian Krzanich, CEO of Intel, announced that "our cadence today is closer to two and a half years than two.” This is scheduled to hold through the 10 nm width in late 2017.He cited Moore's 1975 revision as a precedent for the current deceleration, which results from technical challenges and is “a natural part of the history of Moore's law.”

References

https://en.wikipedia.org/wiki/Moore%27s_law

CMOS Interview Questions Part 1

1.  show the relationship between Vds-Ids fot MOSFET. 
2. show how its characteristics it varies with i. increasing Vgs ii) velocity saturation iii) Channel length modulation iv ) W/L ratio. 
3. Describe body effect also write mathematical expression? 
4. Explain briefly  latch up effect in CMOS design and how will you overcome this effect? 
5. Explain Noise Margin with the help of inverter?
6. how delay varies on  increase load capacitance? 
7. how to minimize power consumption for CMOS logic? 
8. What will happen when the  interchanged PMOS and NMOS with one another in an inverter? 
9. Explain body effect? 
10. What is advantage of NAND over NOR gate in fabrication?
11. Explain briefly Noise Margin and how to determine Noise Margin ?
12. Explain inverter sizing? 
13.  How do you size NMOS and PMOS transistors to increase the threshold voltage? 
14.  if we include a resistance at the output of a CMOS circuit, what will happen? 
15.   Explain limitations of increasing the power to reduce delay? 
16  How does  metal Resistance ovary with increasing thickness and length? 
17. Explain Charge Sharing and its problem while sampling data from Bus? 
18  we need increase the size of inverters in buffer design, why? Explain why we cannot give the output of a circuit to one large inverter? 
19. With Mathematical expression, explain CMOS switching power dissipation? 
20 Why substrate in NMOS connected to ground and  PMOS to VDD? 
21 What are the difference b/w a MOSFET and BJT ? 
22.  Which type transistor has more gain- BJT or MOS and explain with suitable reason? 
23  Why does PMOS and NMOS are  equally size in a Transmission Gates? 
24  Explain metastability, how it will occur? What are different methods to avoid this? 
25 what is zener breakdown?
26   what is avalanche breakdown? 
27 if Vds is increased over saturation, then what will happen?