Wafer Fabrication Techniques

Wafer fabrication is a procedure composed of many repeated sequential processes to produce completeelectrical or photonic circuits. Examples include production of radio frequency (RF) amplifiers, LEDs, optical computer components, and CPUs for computers. Wafer fabrication is used to build components with the necessary electrical structures.

The main process begins with electrical engineers designing the circuit and defining its functions, and specifying the signals, inputs, outputs and voltages needed. These electrical circuit specifications are entered into electrical circuit design software, such as SPICE, and then imported into circuit layout programs, which are similar to ones used for computer aided design. This is necessary for the layers to be defined for photomask production. The resolution of the circuits increases rapidly with each step in design, as the scale of the circuits at the start of the design process is already being measured in fractions of micrometers. Each step thus increases circuit density for a given area.

The silicon wafers start out blank and pure. The circuits are built in layers in clean rooms. First, photoresistpatterns are photo-masked in micrometer detail onto the wafers' surface. The wafers are then exposed to short-wave ultraviolet light and the unexposed areas are thus etched away and cleaned. Hot chemical vapors aredeposited on to the desired zones and baked in high heat, which permeate the vapors into the desired zones. In some cases, ions, such as O2+ or O+, are implanted in precise patterns and at a specific depth by using RF-driven ion sources.

These steps are often repeated many hundreds of times, depending on the complexity of the desired circuit and its connections.

New processes to accomplish each of these steps with better resolution and in improved ways emerge every year, with the result of constantly changing technology in the wafer fabrication industry. New technologies result in denser packing of minuscule surface features such as transistors and micro-electro-mechanical systems (MEMS). This increased density continues the trend often cited as Moore's Law.

A fab is a common term for where these processes are accomplished. Often the fab is owned by the company that sells the chips, such as AMD, Intel, Texas Instruments, or Freescale. A foundry is a fab at which semiconductor chips or wafers are fabricated to order for third party companies that sell the chip, such as fabs owned by Taiwan Semiconductor Manufacturing Company (TSMC), United Microelectronics Corporation (UMC) and Semiconductor Manufacturing International Corporation (SMIC).

Reference

https://en.wikipedia.org/wiki/Wafer_fabrication

Logic Synthesis

What is Logic Synthesis ?

“ Logic synthesis is the process of converting a high-level description of the design into an optimized gate-level  representation, given a standard cell library and certain design constraints “

Why Perform Logic Synthesis ?

1. Automatically manages many details of the design process:

• Fewer bugs

• Improves productivity 

2.  Abstracts the design data (HDL description) from any particular implementation technology

• Designs can be re-synthesized targeting different chip technologies;

E.g.: first implement in FPGA then later in ASIC


3. In some cases, leads to a more optimal design than could be

achieved by manual means (e.g.: logic optimization) 

Logic Synthesis Flow : RTL TO GATES

RTL description:

Design at a high level using RTL constructs.


Translation:

Synthesis Tool convert the RTL description to un-optimized Internal representation.(Boolean form)


Un-optimized Intermediate Representation:

Represented internally by the logic synthesis tool in terms of Internal data structure.

Logic Optimization: 

Logic is optimized to remove redundant logic. 

Technology Mapping and Optimization: 

The synthesis tool takes the internal representation and implements the representation in gates, using the cells provided in the technology library.

Technology Library: 

library cells that can be basic gates or macro cells.


The cell description contains information about the following:


• Functionality of the cell.

• Area of the cell layout.

• Timing information about the cell.

• Power information about the cell.

Design Constraints:

1.Area: 

• Designer can specify area constraint and synthesis tool will optimize for minimum area. 
• Area can be optimized by having lesser number of cells and by replacing multiple cells with single cell that includes both functionality. 

2. Timing: 

• Designer specifies maximum delay between primary input and primary output.

There are three types of critical paths:
I.Path between a primary input and primary output.
II.Path from any primary input to a register.
III.Path from a register to a primary output.
IV.Path from a register to another register


3. Power:

• Development of hand-held devices has led to reduction of battery size and hence low power consuming systems..

Points to note about synthesis 

• For very big circuits, vendor technology libraries may yield non- optimal result. 
• Translation, logic optimization and technology mapping are done internally in the logic synthesis tool and are not visible to the designer. 
• Timing analyzer built into synthesis tools will have to account for interconnect delays in the total delay calculation

Why This Blog Has Been Created

As I did Engineering in Electronics and communication engineering, and i recruited in one of the top service provider company of India in the field of VLSI. I found that tools and methodologies used in the industry is completely different what we used in colleges. Initially it took time to grasp the things. But I was happy that I am working in my own domain. like me many Engineers who are doing there engineering in the field of electronics, and willing to build there career in the core field  (electronics)this blog will be really helpful for them.

             I want to make this blog as forum to build the bridge between college student and industry requirement. Here you can post your doubts or in respective domain, Here i am trying to post the topics which students really need to know to start there career.

Coaching in the field VLSI is really costly and everyone cant afford it. People who wants to make there career, Please use this forum as your initial step. Please post your query and derive maximum advantage of it.

Happy Learning

All The best.......

Warm Regards

VLSI Junction Team