1. What is the use of double spacing and multiple vias?
2. How buffer insertion on victim net can help avoid crosstalk?
3. What is the difference between top level Chip Design and Block level design?
4.How will you place macros in a full chip design?
5. Explain Hierarchical Design and flat design? list down all differences between them.
6. How does design complexity increases, when the operating frequency of the design increases?
7. Have you done physical verification, what all physical design tools you used?
8. How will solve routing congestion exists between macros?
9. on what parameters does die size depends on?
10. What is antenna effect, how can it create problem in design?
11. If the full chip design is routed by 7 layer metal, why macros are designed using 5 metal layer instead of using 7 metal layer?
12. what is the technology node of your project?
13. what is the block size?
14. How many metal layers were there
15. what is the technology nodes, on which you have hands on experience in?
16. What is the hard macros count in your design?
17. What all inputs required to start physical design flow?
18. What is synopsys design constraint (SDC) file contains?
19. Explain the power structure of your design?
20 How will you calculate , macro ring width and strap or trunk width, core ring width?
21. How will you do power planning?)
22. How to find number of power pad and IO power pads?
23. How the width of metal and number of straps calculated for power and ground?
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