1.what all low power techniques you know?
2.how would you control leakage current?
3.what are the ways to reduce dynamic power consumption?
4.What are the factor does dynamic power depends?
5.How will you do power planning?
6.How to estimate the static power
7.How to estimate the dynamic power
8.The number of the core power pad required for each side of the chip core PG ring width
9. How to EM & IR are taken care during power planning stage?
10. How will you handle IR drop and congestion which occurring at the same time ?
11. what are the different methods to reduce IR drop problem?
12. How will you fix setup time problem in reg to reg path?
13. How insertion of buffer help in fixing setup time violation?
14. what all the parameter you will see to qualify floorplan?
15. what do you mean by Aspect ratio?
16. what are the guidelines you will follow for Macro placement
17. what all the challenges you faced in you P&R flow?
18. Explain briefly How to synthesize clock tree, ?
19. How many clocks were present in your project?
20. What all complexity you faced to handle those clocks?
21. Are they come from seperate external resources or PLL?
22. Why buffers are used in clock tree?
23. What do mean by crosstalk cross talk, How to prevent cross talk effect?
24.What is shielding ? how it helps to avoids crosstalk?
25. How do spacing reduces crosstalk effect?
2.how would you control leakage current?
3.what are the ways to reduce dynamic power consumption?
4.What are the factor does dynamic power depends?
5.How will you do power planning?
6.How to estimate the static power
7.How to estimate the dynamic power
8.The number of the core power pad required for each side of the chip core PG ring width
9. How to EM & IR are taken care during power planning stage?
10. How will you handle IR drop and congestion which occurring at the same time ?
11. what are the different methods to reduce IR drop problem?
12. How will you fix setup time problem in reg to reg path?
13. How insertion of buffer help in fixing setup time violation?
14. what all the parameter you will see to qualify floorplan?
15. what do you mean by Aspect ratio?
16. what are the guidelines you will follow for Macro placement
17. what all the challenges you faced in you P&R flow?
18. Explain briefly How to synthesize clock tree, ?
19. How many clocks were present in your project?
20. What all complexity you faced to handle those clocks?
21. Are they come from seperate external resources or PLL?
22. Why buffers are used in clock tree?
23. What do mean by crosstalk cross talk, How to prevent cross talk effect?
24.What is shielding ? how it helps to avoids crosstalk?
25. How do spacing reduces crosstalk effect?
No comments:
Post a Comment